Grid-Connected Multilevel Converter with Optimal Programmed PWM and Virtual Synchronous Machine

Abstract

Optimal Programmed Pulse-Width Modulation (OP-PWM) and its predecessor Selective Harmonic Elimination (SHE) are strong candidates to modulate high-power medium-voltage inverters, since they result in reduced switching losses for a given power quality requirement. SHE can lead to high amplitude harmonic components located at frequencies close to the eliminated ones requiring a bulky filter or increased commutation losses. To overcome these limitations, this chapter proposes the definition of the commutation angles of an OP-PWM from an optimization problem that considers both the limit of the current Total Harmonic Distortion (THD) an its individual low-order harmonic amplitude. On the other hand, primary controllers for grid-connected converters, such as the Virtual Synchronous Machines (VSM) have at their output the amplitude and frequency of the voltage to be synthesized by the converter which, matches with the input of an OP-PWM. This chapter aims to develop an optimized modulation technique for grid-connected converters in accordance with the limits of current harmonic content of the IEEE 1547 standard. Finally, real-time operation of a grid-connected three-phase neutral point clamped converter is carried out in the Hardware-in-the-Loop Typhoon (HIL) 402 to demonstrate the performance of the proposed approach.

Appendices

Appendix A

The search of the switching angles is performed by means of the software MATLAB. The command fmincon finds a constrained minimum of a function of several variables. The fmincon attempts to solve problems of the form:

$$\begin{aligned} \begin{aligned} \min _{} \quad&f(X)&\\ \text {subject to} \quad&AX \le B, \, \, A_{eq}X = B_{eq} \quad&\text {(linear constraints)}\\&C(X) \le 0, \, \, Ceq(X) = 0 \quad&\text {(nonlinear constraints)} \\&LB \le X \le UB \quad&\text {(bounds)} \\ \end{aligned} \end{aligned}$$

(5.36)

where X is a vector that contain the switching angles, f(X) is a function to be minimized, $C_{eq}(X)$ is a restriction that ensures the amplitude of the fundamental harmonic component, the matrices $A_{eq}$ and $B_{eq}$ determine the linear inequality and LB and UB are the upper and lower bounds.

For the proposed algorithm presented as follows, it is defined two functions: the first is fminimize that encompass the variable to be minimized, i.e., the THD and the second is frestric that comprises the variables to be restricted, i.e., THD and individual harmonic components. These harmonic components are constrained according to Table 5.1.

The vector init contains the initialization of the seven switching angles. Whenever one solution is achieved, the initialized angles are refreshed for the new search. If the algorithm cannot find a solution next to the discontinuities of the angles, therefore the initialization angles can be randomized. The lower bound (LB) of the solutions is zero and the upper bound (UB) is $\pi /2$.

Appendix B

Figure 5.19 shows the VHDL code to implement the main part of the proposed modulator for the phase A. A VHDL code usually is composed of processes. These processes are activated by a sensitivity list. There are two signals at the sensitivity list: reset and clock. Reset is used to asynchronously put all variables to default states. On the other hand, an uprising edge clock is used to run the modulator itself.

There are other processes to implement all the functions of the modulator, e.g., dead-time generation, receiving/sending data from/to the DSC, but they are not shown here for the sake of simplicity.

Fig. 5.19

VHDL code to implement the proposed modulation for phase A